1. Field of the Invention
The present invention relates to logic gate structures, and particularly, to a Flash electrically erasable and programmable read-only memory (Flash EEPROM) and its use in a multi-function memory array.
2. Description of the Related Art
Electrically erasable and programmable non-volatile semiconductor devices, such Flash EEPROMs are well known in the art. One type of Flash EEPROM employs metal-oxide-semiconductor (MOS) floating gate devices. Typically, an electrical charge is transferred into an electrically isolated (floating) gate to represent one binary state, while an uncharged gate represents the other binary state. The floating gate is generally placed above and between two regions (source and drain) spaced-apart from each other and separated from those regions by a thin insulating layer, such as a thin oxide layer. An overlying gate is disposed above the floating gate provides capacitive coupling to the floating gate, allowing an electric field to be established across the thin insulating layer. “Carriers” from a channel region under the floating gate are injected through the thin insulating layer into the floating gate to charge the floating gate. The presence of the charge in the floating gate consequently indicates the logic state of the floating gate, i.e., 0 or 1.
Dynamic random access memory (DRAM) devices are also well known in the art. Generally, after manufacture, each DRAM device is tested for quality. Each DRAM device is tested with writing and reading testing patterns from an external memory location into the DRAM device. If defects are detected, the testing system may try to correct the problem by isolating a defective memory row or column and re-routing the data to a redundant memory row or column. The testing and the correction are generally done on some testing machines and the testing patterns and re-routing patterns are read from memory locations provided by the testing machines.